Method to avoid threshold voltage shift in thicker dielectric films

ABSTRACT

A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.09/312,373, filed May 13, 1999, now U.S. Pat. No. 6,462,394; which is acontinuation of U.S. application Ser. No. 08/578,825 filed Dec. 26,1995, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to integrated circuit structures, and inparticular, it relates to dielectric materials used within dynamicrandom access memory cells formed on semiconductor integrated circuits.

2. Background Art

In a conventional transistor a gate is separated from the source anddrain by a dielectric layer. When a sufficient voltage level is appliedto the gate the transistor turns on and current flows between the sourceand the drain of the transistor. In a similar manner, when conductors ofintegrated circuits pass over dielectric layers located above adjacentn-wells or diffusion regions they can cause leakage current to flowbetween the n-wells or between the diffusion regions. This leakagecurrent is very undesirable.

It is well known in the art of semiconductor fabrication that dielectriclayers formed from organic sources can have shifts in their thresholdvoltage due to impurities in the dielectric material. The impurities arepresent in the layer because of the organic processes, such asozone-TEOS based chemistry, which are used to form the material of thedielectric layer.

It is also known for the impurities in the dielectric layer to diffuseand collect at interfaces close to the substrate during high temperatureprocessing steps performed after deposition of dielectric materialformed with organometallic precursors. This diffusion can seriouslydegrade integrated circuit operation.

It is therefore an object of the present invention to provide a processfor forming dielectric material for semiconductor fabrication usingorganic chemistry such as ozone-TEOS based chemistry and organometallicprecursors which leave undesirable impurities in the dielectricmaterial.

It is a further object of the present invention to eliminate or reducethreshold voltage shift caused by impurities that are a consequence ofthe organic processes for forming the dielectric layer.

It is a further object of the present invention to provide such aprocess for BPSG films that are thicker than at least 5 KA.

It is a further object of the present invention to prevent the problemsassociated with diffusion of impurities in dielectric layers tointerfaces near the surface of the substrate.

These and other objects and advantages of the invention will become morefully apparent from the description and claims which follow or may belearned by the practice of the invention.

SUMMARY OF THE INVENTION

A method of fabricating an integrated circuit having reduced thresholdvoltage shift is provided. A nonconducting region is formed on thesemiconductor substrate and active regions are formed on thesemiconductor substrate. The active regions are separated by thenonconducting region. A barrier layer and a dielectric layer aredeposited over the nonconducting region and over the active regions.Heat is applied to the integrated circuit causing the barrier layer toanneal. The dielectric layer can be a. BPSG film. Preferably BPSG filmsare deposited using organometallic precursors. More specifically, ozone(4 to 20% vol conc.), TEOS, TEPO (as an example of a P source) and TEB(as an example of a B source) are reacted at a temperature of at least300° C. such that BPSG films of at least one thousand angstroms areformed at a deposition rate in the range of 500 angstroms/min to 6000angstroms/min using gas or liquid injection for carrying the speciesinto the reaction chamber. The preferred deposition temperature range is300° C.–600° C. The deposition may be done at atmospheric orsubatmospheric pressure, in a plasma or a non-plasma based reactor anddeposition conditions and the dopant concentration can be varied toobtain the desired film properties and composition. Hot wall reactorscan also be used for BPSG film deposition.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the manner in which the above-recited and other advantagesand objects of the invention are obtained can be appreciated, a moreparticular description of the invention briefly described above will berendered by reference to a specific embodiment thereof which isillustrated in the appended drawings. Understanding that these drawingsdepict only a typical embodiment of the invention and are not thereforeto be considered limiting of its scope, the invention and the presentlyunderstood best mode thereof are described and explained with additionalspecificity and detail through the use of the accompanying drawings.

FIG. 1 shows a cross-sectional schematic representation of a prior artsemiconductor integrated circuit which may be used in accordance withthe method of the present invention.

FIG. 2 shows a graphical representation of the threshold voltage shiftin integrated circuits that is solved by the method of the presentinvention.

FIG. 3 shows a cross-sectional schematic representation of thesemiconductor integrated circuit of FIG. 1 including a barrier layerformed in accordance with the method and structure of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1, there is shown a prior art cross-sectionalrepresentation of a semiconductor device 10. Active regions 12 areformed within a silicon layer 18. It will be understood by those skilledin the art that the active regions 12 can be any type of diffusedregions such as n+, p+, n−, or p− regions or collections of transistorsformed within n-wells or p-wells. The active regions 12 are separatedfrom each other by an insulating region 14. It will also be understoodby those skilled in the art that the insulating region 14 spacing theactive regions apart may be, for example, a field oxide region betweentwo diffusion regions, a trench oxide or any other type of isolatingregion. Thus, region 14 can be any kind of insulating region betweenactive areas within an n-well or a p-well. A dielectric layer 20 isdeposited over the active regions 12 and the field oxide layer 14. Thedielectric layer 20 can be formed of, for example, BPSG, BSG, PSG orsilicon dioxide. A lead 26 is located above the dielectric layer 20.During use of an integrated circuit formed with the semiconductor device10 a voltage level on the lead 26 may give rise to a small leakagecurrent 16 between the active regions 12 under the insulating region 14.

Leakage current 16 between isolated active areas in a p-well or ann-well is enhanced by the presence of oxide charges 24 within thedielectric layer 20 upon application of a voltage to lead 26. Whileoxide charges 24 are indicated with “+” in the drawings for illustrativepurposes, it will be understood that oxide charges 24 can be positive ornegative. For example, negative charges can be present with an n-wellstructure and positive charges can be present with a p-well structure.Thus, the leakage current between active areas in an n-well structure isenhanced by the presence of negative oxide charges. If additional oxidecharges 24 are present in the dielectric layer 20 the problemsassociated with oxide charges 24 increase. Thus, when the dielectriclayer 20 is formed with a greater thickness, the problems are increaseddue to the greater amount of oxide charges 24 that are carried by theadditional BPSG or other material of the thicker dielectric layer 20.The oxide charges 24 are a substantial problem for thicknesses over onethousand angstroms.

Referring now to FIG. 2, there is shown a graphical representation 50for a p-type substrate 18. The graphical representation 50 illustratesthe relationship between the voltage applied to the lead 26 and thecapacitance in the dielectric layer 20. If there is no oxide charge 24in the dielectric layer 20 the curve 54 results. If positive charges 24are present in the dielectric layer 20 the flatband shift of curve 52results. If negative charges 24 are present in the dielectric layer 20the flatband shift of curve 56 results.

The primary source of the oxide charges 24 present within the dielectriclayer 20 is contamination of the dielectric layer 20. One of thepotential sources of the contamination in the dielectric layer 20 can becarbon. The contamination of the layer 20 occurs during production ofthe BPSG or other type of material forming layer 20. It is wellunderstood that molecules acting as sources of boron, phosphorous andsilicon atoms must react with oxygen in order to form the BPSG, BSG, PSGor other material of the dielectric layer 20. The contamination of thedielectric layer 20 can thus occur due to the use of organometallicprecursors that can be used to provide the boron, phosphorus, siliconand oxygen atoms of the BPSG of the dielectric layer 20.

For example it is known to form the BPSG material of the dielectriclayer 20 by reacting ozone with organic precursors such as (C₂H₅O)₄Si(TEOS) triethylphosphate (TEPO) and triethylborane (TEB) in order toprovide the required boron, phosphorous, and silicon atoms. Each ofthese molecules is an organic molecule containing carbon atoms. Thecontamination due to the carbon of the organic molecules remains in theBPSG dielectric layer 20 after the reactions forming the BPSG materialand cause impurities in the BPSG layer 20. Furthermore, it will beunderstood that contamination can arise in any other way from theorganic precursors and from any other sources. For example, impuritiesmixed with the organic precursors can cause the contamination. Thecontamination causes the oxide charges 24 to be present in thedielectric layer 20 and, thereby, causes threshold voltage shift. Othercontamination sources can also be present that would give rise tocharged regions in oxide.

It is also known in the prior art to obtain the boron, phosphorus andsilicon atoms required for forming the BPSG or other material of thedielectric layer 20 from sources that are not organic sources and do notcontaminate the layer 20 in this manner. For example, either in thepresence of a plasma or at atmospheric pressure, oxygen may be reactedwith silane (SiH₄), phosphine (PH₃) and/or diborane (B₂H₆) in order toform BPSG.

However, the use of organometallic precursors such as TEOS, TEPO and TEBto form dielectric materials for semiconductor fabrication is preferredto the use of the inorganic materials for several reasons. The organicreactions permit better control of the fabrication process. For example,the organic reactions provide more precise control of doping and oxidethickness. Furthermore, they permit better step coverage.

Referring now to FIG. 3, there is shown a cross-sectional representationof a semiconductor device 100 formed in accordance with a preferredmethod of the present invention. The semiconductor device 100 issubstantially similar to the semiconductor device 10 except for theaddition of a barrier layer 30. The barrier layer 30, is deposited belowthe dielectric layer 20 and above the active regions 12 and theinsulating region 14.

The depositing of layer 20 can be followed by heating the layer 20 to atleast 550° C. In one preferred embodiment rapid thermal processing isperformed. In rapid thermal processing, the temperature of layers 20 and30 is raised to between approximately 850° C. and 1050° C. for at leastfive seconds causing the layer 20 to reflow. In another preferredembodiment the temperature can be raised to approximately 750° C. to1000° C. in a furnace for at least five minutes. During the reflow ofthe dielectric layer 20, and during any other subsequent hightemperature process steps which may occur, the impurities within thedielectric layer 20 may diffuse. For example, without the barrier layer30 the impurities may diffuse to the interface between the dielectriclayer 20 and the active regions 12 and, more likely, to the interfacebetween the dielectric layer 20 and the insulating region 14 and degradethe performance of the integrated circuit. The barrier layer 30 blocksdiffusion of the impurities into the active regions 12 and into theinsulating region 14 during the reflow step and/or any other hightemperature process steps.

The barrier layer 30 can be formed in many different ways. For example,the barrier layer 30 can be a silane-based oxide layer or a silane-basedoxynitride layer. Additionally, the barrier layer 30 can be a nitridefilm which can be formed using plasma technology or using non-plasmatechnology. Additionally, silane-based nitride or nitride with asilane-based oxide stack can be used. Additionally, the layer 30 can bea composite layer formed of layers of silicon dioxide and siliconnitride. Thus, in accordance with the present invention the organicdielectric layer 20 is deposited over any of these barrier layers 30 orbarrier stacks 30. The barrier layer 30 formed in this manner can be inthe range of approximately fifty angstroms to approximately two thousandangstroms. Preferably, it is between one-hundred and one-thousandangstroms.

Prior to depositing the barrier layer 30 and before forming any of thepreviously described stacks a plasma treatment of the semiconductordevice 10 can be performed. The plasma treatment can be a conventionalhigh voltage plasma treatment using oxygen plasma, ozone plasma,nitrogen plasma, ammonia plasma or a combination of the these gases.

It has been determined that the refractive index of materials can serveas an indication of whether they are suitable for forming the materialof the barrier layer 30 of the present invention because the index ofrefraction of these materials is related to their nitrogen content. Therange of satisfactory refractive indices for a material to function asthe barrier layer 30 of the present invention is from approximately 1.5to 2.6. The refractive index of silicon nitride is typicallyapproximately 2.0. The refractive index of oxynitride is typicallybetween approximately 1.46 and 2.0. The refractive index of silicon richoxynitride is between approximately 2.0 and 2.6. The refractive index ofsilicon dioxide is approximately 1.46. The refractive index of acomposite layer 30 formed of silicon dioxide and silicon nitride issomewhere between the indices of the silicon dioxide and silicon nitridedepending on the relative amount of each material used in forming thelayer. Although other barrier materials having a refractive index withinthe range can be used, it will be understood that a material forming thebarrier layer 30 must be structurally sound in addition to having arefractive index in this range. It is thus understood that many othermaterials can be used to form the layer 30. For example, aluminum oxideand aluminum nitride and other insulating materials can be used.

It is to be understood that although the present invention has beendescribed with reference to a preferred embodiment, variousmodifications, known to those skilled in the art, may be made to thestructures and process steps presented herein without departing from theinvention as recited in the several claims appended hereto. For example,the use of the barrier layer 30 is taught under the lead 26 and over theactive regions 12 and the insulating region 14. In one preferredembodiment, the barrier layer 30 of the present invention may bedeposited above n-wells and/or p-wells wherein integrated circuit activeregions are formed in the n-wells and/or p-wells in a conventionalmanner. It will be understood that the method of the present inventionprevents n-well to n-well leakage and p-well to p-well leakage as wellas preventing leakage between active regions within n-wells or p-wells.Furthermore, the method of the present invention may be used to preventmetal field leakage and poly field leakage in general.

1. A method of processing a substrate comprising two active areas and anintervening insulating region, said method comprising: depositing anoxide charge barrier over said substrate; depositing an insulativematerial over said oxide charge barrier, wherein said insulativematerial is less insulative than said barrier; and providing aconductive element over said insulative material, wherein said elementis generally laterally coextensive with said intervening insulatingregion.
 2. The method in claim 1, wherein said step of depositing aninsulative material comprises depositing an insulative material that isallowed to comprise oxide charges.
 3. The method in claim 2, furthercomprising a step of plasma treating said substrate prior to said stepof depositing an oxide charge barrier.
 4. The method in claim 2, furthercomprising: annealing said insulative material; allowing an oxide chargein said insulative material to migrate toward said substrate in responseto said annealing step; and intercepting said oxide charge with saidoxide charge barrier before said oxide charge reaches said substrate. 5.The method in claim 2, further comprising refraining from depositing anyconductive material before said step of depositing an insulativematerial.